Released in 1991 and marketed as a floating-point coprocessor for the Intel 486 SX, the Intel 80487 was actually a fully featured Intel 486 DX with a slightly different pinout. Intel added an unconnected 169th pin as a mechanical key for the 487 Socket. Another pin known as “MP#” (Math Present) was used to entirely disable the original 486 SX by triggering its “back-off” (from bus) mode. Being almost 100% compatible with the 486 DX, supporting the 486 SX with the Universal Chip Analyzer was trivial. I bought many Socket 168 socket and I just drilled a 1 mm hole and it worked immediately.
According to the 487’s datasheet, it was rated at 25 MHz maximum, but it also run fine at 33 MHz. It is possible to detect a B0-step Intel 487 by its unique CPUID (0x421). AFAIK, all retail 487s are B0-Step. A0-step are Engineering Sample only (with an unknown CPUID, maybe 0x420).
While testing the 487, I noticed a strange behavior that will deserve more investigation later. It seems the 487SX needs a longer reset period to initialize properly compared to a standard 486. Technically, it makes sense: this additional delay might be needed to let the original 486SX disable itself and back off properly from the bus (before the 487SX takes full control).