During the beta-testing phase of the Universal Chip Analyzer (UCA), some testers noticed that certain CPUs failed on the UCA while appearing to work on more basic testing devices. To determine whether this discrepancy was due to a flaw in the UCA, I purchased a couple of these simpler testers for comparison. Out of five 6502 CPUs that the UCA had flagged as defective, two passed without any issues on the basic testers. To verify their actual condition, I tested them in a real Apple IIe. Both failed to boot the system, prompting me to analyze their behavior further using a logic analyzer.
To understand why this happens, it’s important to look at how common CPU testers—readily available on eBay and other marketplaces—operate. The simplest type, known as a “NOP Tester,” provides a basic clock signal, often generated by a simple oscillator such as a NE555 timer. It permanently feeds a NOP (No Operation) instruction to the CPU’s data bus, instructing it to do nothing except cycle through all addresses indefinitely. In a 6502, the NOP instruction is represented by 0xEA (in binary: 1110 1010), which is hardwired onto the data bus. If the address bus increments smoothly and continuously, indicated by LEDs displaying changing values, the CPU is considered functional.
More advanced testers, like the ones I purchased, incorporate an EPROM containing pre-programmed test code. These devices use 74HCT245 bus transceivers to drive LEDs that display the 16-bit address bus (A0-A15) and a 74HCT574 flip-flop to control an 8-LED moving dot pattern on the data bus. The ROM feeds instructions to the CPU, allowing for slightly more complex testing than a simple NOP Tester.
However, despite being more sophisticated, EPROM-based testers still fall short of replicating a real computer environment. Unlike a basic tester, an actual computer relies on RAM, external peripherals, and extensive arbitration logic to manage operations. This is why CPUs have so many additional pins beyond just data and address lines. For instance, the 6502 includes bus arbitration signals like READY, IRQ, NMI, READ/WRITE, SYNC, SO, and derived clock signals Ø1 and Ø2. Most cheap testers either ignore or fail to adequately evaluate these critical signals. In contrast, the UCA is designed to comprehensively test every CPU pin, accurately simulating ROM, RAM, stack operations, interrupts, and other essential functions found in real-world systems.
The logic analyzer helped pinpoint the exact issue: the R/W (Read/Write) pin on the two defective 6502s was stuck high (logic 1). This rendered them unusable in real computers and on the UCA, yet they still appeared functional on the basic testers.
This highlights the key weakness of cheap CPU testers: they only assess a limited set of CPU functions, sometimes failing to detect faults that would cause real-world failures. The UCA, by contrast, provides a much more thorough evaluation, ensuring CPUs are genuinely functional under real operating conditions rather than just passing a superficial test.
