Month: February 2018

New milestone reached for the UCA !

After days messing with that prehistoric micro-architecture (don’t even have a CALL/RETURN instruction) as well as the VHDL code to implement the tight timings needed, the UCA now supports the RCA CDP1802 (COSMAC) CPU !

Here is a sample of the preliminary test code used

Testing can be done at 2.5/3.2/4.0 & 5.0 MHz.

The interesting part is that it doesn’t require any additional adapter, just a firmware update. I designed an adapter for this chip, but it wasn’t finally required.

While developing for the RCA 1802, I found a limitation on the iAPX-86 UCAS’ hardware design : it can’t measure current for this particular IC. The 1802 power consumption is abysmall (< 2 mA) and under the lowest end of the range I choose. The UCAS just can’t reliably measure power-hungry behemoths like the HMOS USSR clones (> 1.5W) and extremely low power chip like the 1802. Not really a big deal..

Anyway, it now works as expected with CDP1802! Right now, I don’t have CDP1804/05/06 but I’ll try to find one of each soon to check if they also works. They should also run fine and I will be able to check their specific features (Internal RAM & extended instruction set).

Here are some pictures!

RCA CDP1802D – Tested at 3.2 MHz

Harris CDP1802ACE – Tested at 5.0 MHz

Big milestone! The whole communication between all parts of the UCA (from the MCU synthesized inside the FPGA to the USB port connected on the ATMega) is now working as expected !

I wrote a simple software in C# this night to show how the advanced features will look like. Top-right, you have the current status of the UCA/UCAS with all the embedded firmware version (yep, there is 3 of them!) . Top-left, the obvious “Connect” Button and the current Status (ranging from “testing” to “Pass” or “Fail” and even “short-circuit”).

In the middle Area, all the feature detected by the UCA : bus width (8088 Vs 8086), Burnin Mode and frequency settings, Microcode (TBD), and also Voltage / Current / Power Drawn by the IC and the corresponding process (CMOS/HMOS/…). I should be able to detect stepping and erratas in hardware for some chips Smile

Finally, in the bottom area, an hardware performance test, 100% handled by the FPGA. Right now, I only wrote the FPU test, but the ALU (Int) test will follow. The absolute value are probably not accurate yet, but the relative KFlops is good. As you can see, the NEC V30 is MUCH faster than a good ol’ 8086 for FPU processing. I will fine tune the benchmark code later, but I’m happy with the progress ^_^

UCA Analyzer in tethered mode testing a Sony CXQ70116P-8 overclocked at 12 MHz

UCA Analyzer in tethered mode testing a P8008-2 overclocked at 10 MHz