Since the end of last year, I faced a lot of change in my personal
life: new job, new house, new car, etc. Except my girlfriend, almost everything
else changed in the last 3 months. Damn exciting, but I had very little time to
spend on side projects.
It’s now time to resume the work on the Universal Chip Analyzer! My next goal was to add support for the very successful MOS 6502, an 8-bit microprocessor released in mid-70s that was at the heart of many designs well into the 80s. The original 6501 (circa 1975) was pin-compatible with the M6800 while being much less expensive, but Motorola sued MOS almost instantly and the 6501 has been withdrawn very quickly. The 6502 shares the same internal micro-architecture with the original 6501 but uses a different pin arrangement. It’s a very simple CPU, with a 8-bit accumulator, two index registers and a 16-bit address bus (able to interface with a maximum of 64 KB of memory). The 6502, just like many other early CPU, doesn’t have a specific way to handle I/O: you must define an arbitrary memory-mapped I/O range and configure your hardware accordingly.
Several variants of the MOS 6502 has been launched through
the decade, some of the them with reduced addressable memory (6503 to 6507) and
some others with additional features (6508 to 6510, …). Many early computers
and consoles are based on a 6502: Apple IIe, Commodore 64, Atari 2600, Nintendo
NES, Oric Atmos, etc.
Adding support for the 6502 wasn’t as easy as I expected.
The main issue came from the timings. Usually, I drive all the logic inside the
FPGA with the the clock signal generated locally and sent to the CPU. That doesn’t
work with this particular CPU because it integrates an internal two-phase clock
generator used to sync external IC. So, I finally had to feed these two clocks
back in the FPGA and sync the internal logic with them. Some delays were needed
to match the original timings (FPGAs hate delays) but everything now seems to
Here is the UCA testing a NMOS Rockwell R6502P at 1 MHz and a much more modern CMOS Rockwell R65C02 at 4 MHz (overclocked from 3 MHz):
Testing frequency can be set at 1.0 / 2.0 / 3.0 or 4.0 MHz to match the most popular 65xx
I’m waiting to get some samples to support other 6502-based CPU like 6510 or 28-pin 6503 -> 6507. A Rockwell 65C112 has already been seen working properly. The passive adapter isn’t final now, because I still need to work on my next goal: the Motorola 6800! This CPU Is the last (but not least) big one I need to support with the UCA. Stay tuned!
A new milestone for the Universal Chip Analyzer (U.C.A.) : it now supports Intel 8080s, one of the very early CPU released by Intel in 1974! I originally planned to create a complete UCAS (UCA Shield) to support the 8080, but I was finally able to design a small UCA Adapter for the iAPX86 UCAS.
This is the first “active” UCA adapter (both the adapters for Zilog Z80 & Signetics 2650 are only passive). The biggest issue with the 8080 was the power requirements : unlike all CPU supported so far by the UCA, the 8080 doesn’t work with a single +5V supply rail. It also needs +12V & -5v. +12V has been created from +5V with a TI DC-DC Boost Converter and -5V is generated using a charge-pump IC.
Some signals like the two-phase clock are also not TTL compatibles and requires a true MOS voltage swing (0-12V). For the first alpha prototype, I tried some high-speed transistors as voltage translators, but I wasn’t able to meet the tight rise/fall time (~25 ns) expected by the 8080. I then tried a Dual MOSFET driver and it worked perfectly. All components are packed on a tiny adapter the size of the previous passive ones.
Testing frequency can be set at 2.0/2.6/3.1 or 4 MHz
The expected “retail” price for the 8080 UCAS Adapter is ~$25.
Some news about progress done on the Universal Chip Analyzer :
About the UCA itself (modded Mojo v3 board), I found a reliable source for assembled board and they will be modified soon. All firmware features are now implemented and working correctly. UCA FW v1.00 is close.
About the iAPX86 UCAS, a first batch has been ordered from Elecrow, but they soldered a wrong component on them (well, 50+ wrong components). So I had to send back the whole batch to China. Unfortunately, the package now seems frozen somewhere in China! Tracking is EW001348809FR if you want to check… If it get lost, I will lose $400 and I’ll have to order another batch. Sad.
Anyway, when I got the package from Elecrow, they added two unsoldered PCBs, so I was able to assemble one of them myself to validate the final 1.00 PCB. Good news: everything is working correctly! Signal integrity is much better than on ES/QS, up to 50 MHz, and all hardware bugs are solved. VERY good news. I tested quickly the new expansion port (dedicated for future uses) and it also works as expected.
I’m working on a new UCAS Adapter for the Intel 8080. The goal is to use the iAPX86 Shield to test Intel 8080. They requires +5/+12 & -5V, so the Adapter will be an active adapter, but the 8080 is TTL compatible. The design is done and proto PCB will be ordered soon.
I’m also working on 3 different UCA Shield :
The MOS/MOT UCAS for Motorola 68xx & MOS 65xx CPUs. There is no real technical difficulties on this one from the tech side.
The MCS-4/-40 UCAS for Intel 4004 & 4040. LOT of technical challenge here. Interfacing a 45+ years old PMOS CPU that requires -10V/+5V with a modern 3.3V FPGA is quite hard. Especially while using ONLY modern ICs. I’m still working on the schematics right now, messing with comparators, zeners and transistors. The HDL code will not be easy, but I have some ideas.
A new “Universal PGA Shield” (UPGA). I finally decided to cancel the iAPX-286 Shield that I already showed working on early stages. Why? Because having a 286 UCAS, a 386 UCAS, then a 486 UCAS and another 486 3.3V UCAS, and another 68000/68010/68020/etc. UCAS will be expensive. The UPGA UCAS will support all of them at once, with (quite cheap) interchangeable Sockets. The design have been done, focusing on the fastest 486DX/DX2/DX4. If my design works for them (not proven right now), it will also works with all slower CPUs like 386 or 286. Schematics are done and a nice 4-layer PCB has been designed. It’s a very complex PCB, so I don’t expect the Rev 0.10 to work without massive rework. Fingers crossed!
Now, let me introduce another concept for the UCA : the Xeon ID UCAS! I have big plans for the Universal Chip Analyzer as a truly “Universal” chip analyzer, and this is one of them. Xeons are sometimes hard to identify, especially Engineering Sample (ES are often unmarked, available in various flavor with the same part number, or unknown in databases). Xeon motherboard are also a nightmare to work with, expecting exotic RAM, 2- or 4- CPUs, with BIOS restricted to a few S-Spec. Fortunately, “True” Xeon – like MPs but not the rebranded Desktop CPUs – comes with an embedded “PIROM” chip, used by the motherboard to check their specs without booting the whole CPU. The “Xeon ID UCAS” uses that PIROM to ID the unknown Xeon.
The Shield interfaces with Socket probes to connect with the CPU. Right now, I have a working Socket 603/604 Probe and a LGA1567 Probe, but the UCAS should also work with Pentium II/III Xeon (Slot 2) and up to modern Xeon (LGA2011/3467).
Many information can be grabbed that way. Here is an example with a quite-old Xeon (Gallatin) QF75 ES :
And here with a later Xeon (Tulsa) QQBB ES (Intel Xeon 7140M) :
I also made a small video to let you see how it works:
That’s only a proof-of-concept right now, and the Socket Probe will not be cheap if ever sold, but it looks quite nice 🙂
After days messing with that prehistoric micro-architecture (don’t even have a CALL/RETURN instruction) as well as the VHDL code to implement the tight timings needed, the UCA now supports the RCA CDP1802 (COSMAC) CPU !
Here is a sample of the preliminary test code used
LDI $10 ; LOAD 10h into D
PLO R4 ; Push D in low byte R4
LDI PTRN ; LOAD byte xxh (the pattern memory location) to D
PLO R2 ; Push low order byte from D to R2 (=X)
OUT 1 ; Output the **memory location** at X (=R2) to Port 1 (N0 = 1 / N1-2 = 0)
LDI TLOOP ; LOAD loop constant to D
PHI R3 ; Push D in R3's (=X) high order byte
DEC R3 ; Decrement R3
GHI R3 ; Push high order byte from R3 to D
BNZ LOOP ; if D/R3 not zero, loop until zero
LDI PTRN2 ; LOAD byte xxh (the pattern memory location) to D
PLO R2 ; Push low order byte from D to R2 (=X)
OUT 1 ; Output the *memory location* at X (=R2) to Port 1 (N0 = 1 / N1-2 = 0)
LDI TLOOP ; LOAD loop constant to D
PHI R3 ; Push D in R3's (=X) low order byte
DEC R3 ; Decrement R3
GHI R3 ; Push high order byte from R3 to D
BNZ LOOP2 ; if D/R3 not zero, loop until zero
DEC R4 ; decrement R4 (test loops)
GLO R4 ; put high-byte R4 into D
BNZ TEST1 ; if R4/D is not zero, loop again, if zero, continue to next test.
Testing can be done at 2.5/3.2/4.0 & 5.0 MHz.
The interesting part is that it doesn’t require any additional adapter, just a firmware update. I designed an adapter for this chip, but it wasn’t finally required.
While developing for the RCA 1802, I found a limitation on the iAPX-86 UCAS’ hardware design : it can’t measure current for this particular IC. The 1802 power consumption is abysmall (< 2 mA) and under the lowest end of the range I choose. The UCAS just can’t reliably measure power-hungry behemoths like the HMOS USSR clones (> 1.5W) and extremely low power chip like the 1802. Not really a big deal..
Anyway, it now works as expected with CDP1802! Right now, I don’t have CDP1804/05/06 but I’ll try to find one of each soon to check if they also works. They should also run fine and I will be able to check their specific features (Internal RAM & extended instruction set).
Big milestone! The whole communication between all parts of the UCA (from the MCU synthesized inside the FPGA to the USB port connected on the ATMega) is now working as expected !
I wrote a simple software in C# this night to show how the advanced features will look like. Top-right, you have the current status of the UCA/UCAS with all the embedded firmware version (yep, there is 3 of them!) . Top-left, the obvious “Connect” Button and the current Status (ranging from “testing” to “Pass” or “Fail” and even “short-circuit”).
In the middle Area, all the feature detected by the UCA : bus width (8088 Vs 8086), Burnin Mode and frequency settings, Microcode (TBD), and also Voltage / Current / Power Drawn by the IC and the corresponding process (CMOS/HMOS/…). I should be able to detect stepping and erratas in hardware for some chips Smile
Finally, in the bottom area, an hardware performance test, 100% handled by the FPGA. Right now, I only wrote the FPU test, but the ALU (Int) test will follow. The absolute value are probably not accurate yet, but the relative KFlops is good. As you can see, the NEC V30 is MUCH faster than a good ol’ 8086 for FPU processing. I will fine tune the benchmark code later, but I’m happy with the progress ^_^
UCA Analyzer in tethered mode testing a Sony CXQ70116P-8 overclocked at 12 MHz
UCA Analyzer in tethered mode testing a P8008-2 overclocked at 10 MHz
Some IC families requires a remap of power lines, much harder to implement into the target UCAS then a remap of signal lines. Adding the required hardware to support software power lines remapping on a 40+ pins IC is just too expensive to consider. The solution is a cheap passive adapter (less than $10).
Here is the first one, that add support for Z80 to the iAPX86 UCAS !
Z80 UCAS Adapter The PCB is cut to allow easy manipulation of the underlying Socket’s lever.
Z80 UCAS Adapter mounted on iAPX86 UCA A clear indication of the family supported is printed on top.
Early Zilog Z80A under testing on Z80 UCAS Adapter @ 4 MHz
The Shield can be configured for 2.5/4/6 or 8 MHz. Tested at 8 MHz with a Z80H and working fine!
Good news, the complete MCS-51 support is done! No hardware mod required. Works as-is on the iAPX-86 UCAS.
I did some tests on a lot of different HMOS/CMOS chips, from the 80s to modern ones : 8031, 8032, 8044, 8051, 8052, and up to 80C521. Newer implementations (like the DS80C320 “clock-tripled”) also works fine. After some tuning, I was able to run that MCU at 40 Mhz !
Here are some pics :
AMD 80C521 ES – Tested at 12 MHz
Intel P87C51 Q7805 ES – Tested at 24 MHz
Maxim/Dallas DS80C320-MCL+ – Tested at 40 MHz
Maxim/Dallas DS80C320-MCL+ / Decent clock signal at 40 MHz
Intel TN80C32 – Tested at 12 MHz / Also fine with PLCC Socket !
Last but not least, here is a video I just recorded :
The speed difference at same clock frequency between old & new MCS-51 is amazing !
I’m so excited to finally disclose my project here for the first time. I know only very people may have any interest in this kind of stuff, but as fellow collectors, you’re certainly in those ones. The idea came to my mind last summer, when I read one of the amazing announcement from molka. I realized that, even if I have some skills in electronics and product design, I don’t have any clues about how earliest CPUs worked back in the 70s & 80s. So, I started to study one of the most successful architecture from that era, the Intel 8086. After some basic experimentation on a breadboard, I then started thinking about an ambitious “universal” IC tester and how to build it.
The Ideal Specs
Ideally, I wanted the specification to be as such:
Versatile: Able to check the working condition of many different ICs. As much as possible. CPUs, of course, but also other kind of chips like microcontrollers, BSPs, RAMs, and why not FPUs or other support chips. Sounds like crazy because all these ICs are totally different beasts from an electrical interface point of view. Even a 8086 is vastly different from a 8085.
Advanced: With two testing modes. One basic testing mode, that only requires the UCA and a standard USB power bank to provide the 5V required. You get the result on built-in LEDs. And also one more advanced “analyzer” mode, with the UCA tethered to a computer with USB. With an app, you can get some additional information like real-time power composition, chip identification, working condition, and maybe TBD stuff, depending of the kind of IC tested. On top of that, I also wanted to have “advanced” features. I.e.: testing the working condition of an IC is nice, but testing it at its rated clock frequency is even better. What about overclocking? Benchmark? Could be great too.
Secure: I’m a CPU collector and I don’t want to burn a costly ES if something goes wrong. The UCA need to be able to detect short-circuit or other defaults. Safety first!
Compact: I didn’t want a bulky tester. I tried to keep it as small as possible. The actual footprint (8×6 cm) is barely bigger than a credit card.
Upgradable: Most of the “intelligence” must be in software. The upgradability of the UCA was mandatory. I wanted to be able to upgrade the firmware via USB, to add support for new chips without any (or too much) hardware modifications. More interesting, I also wanted to let the user write his OWN code for the target CPU. So, the UCA can act as a development board.
Future-proof: When I started my first experiments with the 8088, I had to buy and mess around with Intel 8284 clock generator, bus controllers and other support chips. Some of them aren’t manufactured anymore since decades, are hard-to-find and/or expensive. I wanted to get rid of ANY obsolete chips and I’m only using modern ICs widely available.
Affordable: From a technical view, everything I described is close to a device I already own, the Galep-5 Universal EEPROM programmer. It’s a very nice piece of hardware but it costs more than 500€ (and that’s without the numerous expensive adapters often required). I’m not exactly a rich man so I had to keep the price as low as possible. The U.C.A. doesn’t use fancy components. The total BOM is lower than $50. Of course, the final price also depends on manufacturing costs. The fewer I order, the higher the price will be.
So here we are. From all the crazy specs described previously, only a few are working right now. I’m not pretentious enough to tell that all of them will work one day, but the current progress seems to prove the whole project isn’t a total failure. A pretty good start!
How It Is Built
Let’s talk about the UCA. The most obvious central component to use is an FPGA. Microcontrollers are just too slow to interface at full speed with even a 8086 from the 80s, and I have more ambitious target CPU in mind. FPGAs have a lot of IO pins and can be software reconfigurable to accommodate a variety of pinouts. They’re also extremely fast. Main issue (at least for me): developing FPGA and writing HDL code is a nightmare. We’re clearly not in the same world as Arduino or Raspberry Pi.
Developing a compact FPGA PCB with 100+ I/O is not extremely complex, but it’s not cheap. You must use a 4-layer PCB (or more) and solder a fine-pitched QFP or BGA IC. In small quantities, the price skyrockets very quickly. So, I looked at the FPGA development boards already available in the market. No need to reinvent the wheel if something suitable was already created and mass-produced. All the UCA’s intelligence is inside the HDL code that emulates (almost) everything and doesn’t require fancy electronics. I found the perfect board: The Mojo from Embedded Micro. It was a successful Kickstarter project launched in 2013 that raised more than $100k.
The Mojo is a simple board packed with an Atmel ATMEGA 32U4 microcontroller, 4 Mb Flash EEPROM and a Xilinx Spartan 6 FPGA. To fit my needs, I modified the original Mojo to add 128 Mb of EEPROM Flash and a stronger voltage regulation. That only requires swapping some components but doesn’t need any PCB modifications, so I was able to keep the original PCB layout. Of course, the original Mojo firmware burnt into the ATMega32U4 had to be rewritten, as well as the original FPGA firmware upload tool.
We now have the UCA itself. Then we need an interface to old chips. Modern FPGAs require 3.3V while most IC introduced before mid-90 use 5V (or much higher voltages for the pre-TTL era). The idea here is to use another PCB plugged on top of the UCA (called “UCA Shield” or UCAS). The UCAS is a low-cost, removable PCB. It can be switched to another one to support other IC family. Some UCAS can support many different chips, just by setting a DIP switches. Some chips works without any other modification, just by plugging them into the ZIF Socket, some will require a (very) cheap adapter on top to accommodate different packages (PLCC, LCC, etc.) or different power pinouts.
About the UCA, I successfully modified the original Mojo hardware. The firmware has been rewritten to work with the new EEPROM, supports many different FPGA configuration slots (up to 32 right now). I also added many tweaks (automatic detection for shield swap/DIP setting change, A/D converter modification, etc.). The firmware update tool has also been adapted for the UCA. There is still some work required, but the platform is quite stable right now. The whole process of building/uploading/loading FPGA configuration on multiples slot is almost done. Right now, I didn’t start working on the “tethered” part. I added some functions on the UCA firmware, but the Windows part has yet to be done.
About the UCA Shields (UCAS), the whole project started with the iAPX 86 UCAS. The current revision for that Shield is 0.7 and all the most important hardware parts are working as expected. After 3 months of intensive testing, I found some additional tweaks that must be added. Most of them are dedicated to ease the support for some IC. One (maybe two) revisions of the PCB will be required before the “final” one.
Right now, the iAPX 86 UCAS is able to fully test all 8088 and 8086. Clock frequency can be set to 4 MHz (slowest commercially available freq), 8 MHz (8086-2), 10 MHz (8086-1) and 12.5 MHz (overclocking or some Harris parts). 8088s are tested using a 8-bit interface, 8086s with a 16-bit data bus (autodetected). NEC V20/V30 are of course also supported (and detected with the DIAG button). 8018x will require a UCAS Adapter because they use a different Socket. I didn’t start working on this one, but it’s pretty trivial. To validate the concept of complete reconfiguration, I worked on support for 8085 on the iAPX 86 UCAS. All 8085s can now be fully tested just with a different DIP Switch setting. I’m now working on other type of IC (MCS-51, Z80, etc.). Right now, I can’t guarantee any of them will work, but I’m confident they will.
As a proof-of-concept and to demonstrate the power of the FPGA-powered UCA, I also worked on a iAPX 286 UCAS. The revision 0.1 is done and works as expected. It can test any 80286 in PGA/PLCC/LCC. It still lacks almost all advanced features and need a lot of optimization, but it’s only a matter of time. A 386 UCAS is also possible after this one, and perhaps also a 486 UCAS. The main issue is the space required by the ZIF Socket. But I still have a LOT of work before thinking at 386 and newer CPUs…
Some other UCAS are also in the pipe (4004/4040/8008/8080, RAM UCAS, etc.) but I really need to finalize the current shields before starting other ones. That will be a LONG process, probably spread on several years.
Want to Know More?
There is still gazillions of details I would love to share, but I’ve crossed the TL;DR line since a very long time. For the few of you that want to know more, I just started a website describing the project further. It’s far from being finished but you can probably grab some more information there.